1. Field of the Invention
The invention relates generally to a data decoding and, more specifically, to an 8b/9b decoding scheme for reducing crosstalk on a high speed parallel bus.
2. Description of the Related Art
Many physical bus interfaces implement a high speed parallel bus architecture. For example, the JEDEC specification for GDDR5 (Graphics Double Data Rate) SGRAM (Synchronous Graphics Random Access Memory) defines a thirty-two bit wide parallel data bus (DQ<31:0>). High speed parallel bus architectures are susceptible to various signal integrity issues, including: inter-symbol interference (ISI), simultaneous switching output (SSO) noise, and crosstalk (XTalk). ISI is a form of interference where one symbol (i.e., data word) interferes with subsequent symbols transmitted over the interface during subsequent clock cycles, such as through multi-path propagation (for wireless transmission mediums) or the inherent frequency response of an Input/Output driver and transmission channel. SSO is a form of interference where the simultaneous switching of enough transistor outputs will cause a local ground potential to be higher than a board ground potential (i.e., “ground bounce”) that can result in a logic-low level output at the transceiver to be interpreted as a logic-high level input at the receiver. XTalk is a form of interference where transmission of a signal on one line or circuit causes interference with a symbol transmitted on another proximate line or circuit.
The problems causes by signal integrity issues may be attenuated by taking certain precautions in the design of the circuit. The physical layout of the parallel bus trace lines may be designed to reduce coupling between the traces (e.g., by increasing the spacing between traces or by running a ground trace in between adjacent traces of the data bus). Circuit elements may be designed to actively combat signal interference such as changing capacitors and terminal resistors of the circuit, adding a pre-emphasis filter to the transceiver, or adding active noise cancellation circuitry to the circuit. However, many of these solutions add to the expense of the device (by the addition of more circuit elements) or are insufficient due to the practical limitations of the design (size restrictions). Another solution is to encode the data symbols being transmitted over the bus to limit the effects of crosstalk and SSO. For example, the data bus defined by the GDDR5 SCRAM specification implements a type of encoding called Data Bus Inversion (DBI) where the interface counts the number of low bits in a data symbol and inverts all of the bits in the data symbol if the number of low bits is above a threshold value. DBI helps with the overall power consumption of a circuit by minimizing the number of lines in the bus that are driven low.
One drawback to these techniques is that the costs associated with adding elements to the circuit are prohibitive. Modifying the design, such as by changing dimensions of traces or adding active cancellation elements, may be prohibitive. Another drawback is that conventional encoding techniques such as DBI do not adequately address signal integrity issues caused by crosstalk.
As the foregoing illustrates, what is needed in the art is an improved technique for reducing cross talk over a high speed parallel bus.